In a typical memory system of a computer system, a memory controller facilitates the access of a memory module in the computer system. The memory module may include one or more memories. These one or more memories are also called ranks. The memory controller transmits a host of signals to the ranks including address signals, control signals, clock signals, etc., to access data from the ranks or to send data to the ranks. To send and receive correct data to and from the ranks, the memory controller trains (modifies) the command-address (C/A) signals with respect to a clock signal.
Typically, the memory controller trains the C/A signals by transmitting a particular C/A signal with respect to a clock signal to the ranks and then analyzing a response from each rank to ascertain if the rank correctly received the particular C/A signal. Upon a successful/correct response from the rank, the memory controller delays the phase of the particular C/A signal with respect to the clock signal and then re-transmits the delayed particular C/A signal with a delayed phase to the rank. The memory controller then analyzes a response from the rank to ascertain if the rank correctly received the delayed particular C/A signal. If no response (or an incorrect response) is received from the rank to the memory controller, the memory module transitions to an unknown state (indeterminate state) resulting in a non-functional memory module.
In case of a Double Data Rate 3 (DDR3) memory interface between the memory controller and the memory module having the ranks, the unknown state of the memory module is resolved to a known state by a Joint Electron Devices Engineering Council (JEDEC) standardized initialization process. The JEDEC standardized initialization process results in resetting the memories.
The JEDEC standardized initialization process is a time consuming process that takes several milliseconds for the memory controller to restore the memory module to a known functional state. As computing requirements by users are becoming more memory usage intensive, any error in the memory system e.g., error caused by a C/A signal (with a phase with respect to a clock signal that results in accessing incorrect data from the memory module to the memory controller) results in loss of time due to the time consuming JEDEC standardized initialization process which is required for the DDR3 based memory interface. Furthermore, as demand for faster boot-up of memory systems is increasing, such errors may lead to intolerable lengthening of boot-up time as experienced in a DDR3 based memory interface.